1. Field
This disclosure relates generally to memories, and more specifically, to a memory having a self-timed bit line boost circuit and method therefor.
2. Related Art
Static random access memories (SRAMs) are generally used in applications requiring high speed, such as memory in a data processing system. Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters. The SRAM cell is only stable in one of two possible voltage levels. The logic state of the cell is determined by whichever of the two inverter outputs is a logic high, and can be made to change states by applying a voltage of sufficient magnitude and duration to the appropriate cell input. The stability of a SRAM cell is an important issue. The SRAM cell must be stable against transients, process variations, soft error, and power supply fluctuations which may cause the cell to inadvertently change logic states. Also, the SRAM cell must provide good stability during read operations without harming speed or the ability to write to the cell.
However, good read stability can make it difficult to write to the memory cells. Also, process variations can cause some cells of the array to be more difficult to write than others. One way to have both good write performance and good read stability is to lower the power supply voltage for write operations. Changing the power supply voltage during write operations requires precise timing to insure effectiveness without impacting write operation cycle time significantly. Changing the supply voltage too early is ineffective and changing the supply voltage too late increases cycle time.
Therefore, what is needed is a memory, and a method for operating the memory, that solves the above problems.